Job Description

Analog Layout EngineerJob description: Experience in manual full-custom Analog layout of IC in CMOS/Bi-CMOS process.
Experience with high frequency layout
design verification and debugging such as DRC, ERC, ESDDRC, LVS, ANTENNA DRC, using verification tool such as PVS.
Floor planning from sub-block to chip top level
Very organized and result oriented
Very good understanding of matching techniques

Apply for This Position

Ready to take the next step? Click the button below to submit your application.

Submit Application