Job Description
GHz range)
Analyzing the timing reports and identifying both design and constraints related issues.
Worked on blocks/So C with multiple power and voltage domains
Preferred EDA tool experience: Primetime, Tweaker/Prime Closure, Genus/Innovus/Fusion Compiler
Good Understanding of DFT modes/DFT architecture to debug MMMC timing violations
Good understanding of physical design flow and ECO implementation
Strong understanding of SDC constraints & AOCV/POCV concepts.
Strong TCL/scripting knowledge.
Desirable :
Strong debugging, analysis/problem solving and presentations skills.
Take initiative towards Design/Dataflow Understanding and drive design changes/flow enhancements for faster convergence
Interaction with all stake holders which includes weekly status reporting, issue tracking and resolution.
Project management experience.
Analyzing the timing reports and identifying both design and constraints related issues.
Worked on blocks/So C with multiple power and voltage domains
Preferred EDA tool experience: Primetime, Tweaker/Prime Closure, Genus/Innovus/Fusion Compiler
Good Understanding of DFT modes/DFT architecture to debug MMMC timing violations
Good understanding of physical design flow and ECO implementation
Strong understanding of SDC constraints & AOCV/POCV concepts.
Strong TCL/scripting knowledge.
Desirable :
Strong debugging, analysis/problem solving and presentations skills.
Take initiative towards Design/Dataflow Understanding and drive design changes/flow enhancements for faster convergence
Interaction with all stake holders which includes weekly status reporting, issue tracking and resolution.
Project management experience.
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