Design Verification Engineer - UVM, Verilog (5 to 8 yrs)

**Meet the Team**

We are part of the Hardware Platform Group, with our team specializing in FPGA verification. Our work spans both sophisticated data-path and challenging control-path FPGAs. The verification process includes crafting the DV architecture, test plan, and coverage plan, all the way through to final DV sign-off. We leverage industry-standard tools for simulation, linting, coverage, and assertions, incorporating various quality metrics to ensure a robust process. Our ultimate goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote teams based in SJC and

**Your Impact**

+ As a design verification engineer, develop robust test benches, coverage plans, and constrained random tests.
+ Ensure high-quality and reliable FPGA/ASIC designs through sophisticated verification techniques and comprehensive debugging.
+ Contribute to the adoption and evolution of ground breaking verificatio...