FPGA Power Integrity & Reliability Engineer

Responsibilities

• As a key member of Global Reliability Team you will be responsible for all aspects of FPGA power intent and reliability.
• Responsibilities include power intent verification using UPF, power electrical rule checking, EM and IR closure, timing derating flows, aging, and die package bump and ball intent and planning.
• Good cross functional collaboration needed to verify, debug, and sign off system level reliability items.

Qualifications

• BS/MS in Electrical Engineering
• Circuit design experience for minimum of 2 years
• Familiar with Spice analysis
• Experience with UPF, Verdi, Redhawk, power IR/EM, physical design, and power on sequence is a plus
• Comfortable with PERL/Python, TCL, Linux Shells
• Excellent execution and strong drive to close complex design issues
• Good communication and presentation skills to enable cross functional interaction
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