Physical Design & Flow Methodology Engineer

This role sits at the core of Quadric’s physical design and delivery engine. You will own PPA optimization, build scalable RTL-to-GDSII flows, and directly support customers integrating Quadric’s GPNPU into their SoCs. It’s a hands-on role that combines deep physical design expertise with real-world impact — influencing architecture decisions, enabling customer tapeouts, and ensuring the IP meets aggressive performance, power, and area targets across nodes. If you prefer pure back-end execution with no ownership, this isn’t it.

Responsibilities

PPA Optimization & Analysis

• Drive PPA optimization (timing, area, leakage, dynamic power) across process nodes and hardware configurations
• Apply low-power techniques (clock gating, multi-Vt, operand isolation) and tune synthesis/P&R to meet frequency and area targets
• Characterize design space and build PPA models to support customer evaluations and pre-sales
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