Senior FPGA Engineer (VHDL/Verilog)

Work Arrangement: This role is based in Schelle, Belgium, with the possibility of hybrid work. Applicants must already have the legal right to work in Belgium. Visa sponsorship or work permit support is not available.

Role Overview

As a Senior FPGA Engineer, you will contribute to the development of key components within advanced networking systems, including SmartNICs and hybrid optical switches. You will be responsible for designing and optimizing VHDL and/or Verilog implementations, followed by verifying your designs through simulation using Python-based test cases and scenarios.
You will integrate your designs and IP cores into FPGA projects, perform timing analysis, and conduct on-target verification. Additionally, you will collaborate closely with software and networking teams on system-level performance testing and debugging.

Requirements

Requirements

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