Senior FPGA Full-Chip Timing Engineer

A leading technology firm in Penang is seeking an experienced Full Chip Timing Engineer to develop timing methodologies and execute full-chip timing for next-generation products. The role requires a minimum of 5 years of relevant experience, specifically in SoC development and static timing analysis, along with expertise in tools such as Liberty and Verilog. Candidates will work in a dynamic environment as part of a high-performance design team and are expected to communicate technical trade-offs effectively.
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