Job Description
Overview
We are seeking a highly skilled
Senior Physical Design Engineer
with strong hands-on expertise in
Place & Route (PNR), Synthesis, and Signoff flows . The ideal candidate will have deep knowledge of
timing closure, power analysis, and physical verification , along with exposure to
low-power design methodologies (UPF) .
Key Responsibilities
Execute full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimization
Drive timing closure with a strong focus on
Static Timing Analysis (STA)
Manage signoff activities including:
STA (Setup/Hold closure)
Physical Verification (DRC/LVS)
IR Drop and EM analysis
Perform logic synthesis ensuring timing, power, and area targets are met
Conduct and analyze VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check)
Collaborate with RTL, DFT, and backend teams for design convergence
Debug and resolve tim...
We are seeking a highly skilled
Senior Physical Design Engineer
with strong hands-on expertise in
Place & Route (PNR), Synthesis, and Signoff flows . The ideal candidate will have deep knowledge of
timing closure, power analysis, and physical verification , along with exposure to
low-power design methodologies (UPF) .
Key Responsibilities
Execute full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimization
Drive timing closure with a strong focus on
Static Timing Analysis (STA)
Manage signoff activities including:
STA (Setup/Hold closure)
Physical Verification (DRC/LVS)
IR Drop and EM analysis
Perform logic synthesis ensuring timing, power, and area targets are met
Conduct and analyze VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check)
Collaborate with RTL, DFT, and backend teams for design convergence
Debug and resolve tim...
Apply for This Position
Ready to take the next step? Click the button below to submit your application.
Submit Application