Job Description
Job Title: Senior RTL Design Engineer (ASIC/SoC)
(with DDR/LPDDR/MIPI exp)
Location : Bangalore, Indi
aExperience : 4+ Year
sNotice Period : 30–45 Days (Preferred
)
Role Overvie
w:We are looking for a highly skilled and motivated ASIC RTL Design Engine er to join our team in Bangalore. You will be responsible for the microarchitectu re, design, and implementation of complex digital IP blocks and subsystems. The ideal candidate will have strong expertise in high-speed interface protocols and a proven track record of delivering high-quality RTL within the ASIC/SoC design flo
w.
Key Responsibilit
- iesMicroarchitecture Definit
- ionRTL Implementat...
Apply for This Position
Ready to take the next step? Click the button below to submit your application.
Submit Application