Senior SOC Timing Engineer – FPGA/SoC Signoff

Altera is hiring for the position of SOC Timing Engineer in Bayan Lepas, Penang, Malaysia. The candidate will be responsible for timing closure and signoff of FPGA/SoC and subsystem timing, requiring collaboration with design and architecture teams for timing analysis.

Ideal candidates should have a BE/MS/PhD in Electronics/Electrical Engineering with over 7 years of experience, proficiency in EDA tools like Primetime, and strong analytical skills. This position ensures a dynamic work environment with opportunities for professional growth.