SOC Verification Engineer

Fresh graduates are welcome to apply

• Pre-silicon RTL verification of block, IP and top-level SOC using best-in-class verification methodology
• Develop reusable testbench and verification environment in SV UVM
• Create verification plan from specification and in coordination with architects
• Create directed and constrained random test case to verify functional correctness and performance of the design
• Own and debug failures in simulation to root-cause problems
• Co-work with Architecture/ Design/Validation/SW teams. Own cross functional debug and drive issues to closure

• Bachelor Degree in Electronics Engineering with 6 years or Master's with 3 years of experience
• Expert in Front End Verification using best-in-class verification methodology SV-UVM
• Should have developed SV-UVM test benches for multiple projects
• Parti...