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Sr Staff Verification Engineer ( 数字验证工程师)

📍 Renesas Electronics • Shanghai, Shanghai, China • Posted June 26, 2026

Full-time Posted June 26, 2026
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Job Description


Job Description
  • Understanding the expected functionality of designs.
  • Designing and developing verification environment
  • Improve the verification architecture and flow
  • Running RTL and gate-level simulations/regression.
  • Code/functional coverage development, analysis and closure.

    • Qualifications
  • Bachelor degree or master degree in CS/ME.
  • Minimum of 8 years’ experience.
  • Candidate should be familiar with as System Verilog, UVM verification.
  • Have Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
  • Independent and self-managing.
  • Familiar with UVM source code or key UVM mechanism
  • Familiar with industry standard verification tools and flow.
  • Familiar with basic computer architecture

    • Additional qualifications include:

  • Good IC verification skills and basic knowledge of logic and circuit design, good communication and probl...

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