SystemVerilog/UVM Verification Engineer (FPGA)

Lattice Semiconductor in Bayan Lepas, Malaysia is seeking a skilled verification engineer to develop test plans and verification environments for cutting-edge programmable devices. The ideal candidate will have a BS/MS/PhD in Electronics or Computer Engineering and at least 2 years of experience with SystemVerilog/UVM.

Key responsibilities include creating and debugging tests, implementing coverage metrics, and collaborating with remote designers. Candidate should possess strong analytical and communication skills.